Integrated circuits (ICs) include a multitude of transistors formed on a semiconductor substrate. Various methods of forming transistors on a semiconductor substrate are known in the art. Generally, transistors are isolated from each other by insulating or isolation structures.
One process for forming insulating structures and defining source and drain regions is a shallow trench isolation (STI) process. A conventional STI process typically includes the following simplified steps. First, a silicon nitride layer is thermally grown or deposited onto the silicon substrate. Next, using a lithography and etch process, the silicon nitride layer is selectively removed to produce a pattern where transistor source/drain areas are to be located. After patterning the source/drain areas, the substrate is etched to form trenches. After the trenches are formed, a liner is thermally grown on the exposed surfaces of the trench. The liner is typically an oxide material (e.g., SiO2) formed at a very high temperature in a hydrochloric (HCl) acid ambient. An insulative material, such as, silicon dioxide (SiO2), is blanket deposited over the nitride layer and the liner within the trench. The insulative material is polished to create a planar surface. The nitride layer is subsequently removed to leave the oxide structures within the trenches.
Shallow trench isolation (STI) structures are utilized in strained silicon (SMOS) processes to separate NMOS (N-channel) and PMOS (P-channel) transistors. SMOS processes are utilized to form strained layers that increase transistor (MOSFET) performance by increasing the carrier mobility of silicon. Increasing carrier mobility reduces resistance and power consumption and increases drive current, frequency response and operating speed. Strained silicon is typically formed by growing a layer of silicon on a silicon germanium substrate or layer.
The silicon germanium lattice associated with the silicon germanium substrate is generally more widely spaced than a pure silicon lattice, with spacing becoming wider with a higher percentage of germanium. Because the silicon lattice aligns with the larger silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another.
Relaxed silicon has a conductive band that contains six equal valence bands. The application of tensile strain to the silicon causes four of the valence bands to increase in energy and two of the valence bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus, the lower energy bands offer less resistance to electron flow. In addition, electrons meet with less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon compared to relaxed silicon, providing an increase in mobility of 80% or more for electrons and 20% or more for holes. The increase in mobility has been found to persist for current fields up to 1.5 megavolts/centimeter. These factors are believed to enable a device speed increase of 35% without further reduction of device size, or a 25% reduction in power consumption without a reduction in performance.
Complementary metal oxide semiconductor (CMOS) IC's utilize NMOS and PMOS transistors. NMOS transistors are generally provided in P-type wells or on a P-type substrate. P-channel transistors are generally provided in N-type wells disposed in a P-type substrate. Generally, STI structures separate transistors in N-type wells from transistors in P-type wells.
The STI liner (typically an oxide liner) can create stress in the channel associated with N-type and P-type transistor. However, if the same liner (the same material and/or the same thickness) is utilized for both N-type or P-type transistors, the stress created by the STI liner is different for the N-type transistors than it is for the P-type transistors. For example, an oxide liner may be more beneficial for stress in one type of N or P-doped region than in another type of N or P-region of a CMOS IC. Differentiated stress between N and P-type regions affects the operational characteristics of the N and P-type transistors.
Thus, there is a need for an STI liner fabrication scheme which creates similar stress in P-type and N-type regions. Further still, there is a need for a process of forming high quality oxides for N and PMOS regions with superior stress. Further still, there is a need for a differentiated SMOS trench liner formation process for CMOS processes. Further still, there is a need for an STI process that utilizes different materials or thickness of liners according to NMOS and PMOS transistor locations. Yet further, there is a need for an IC with differentiated liners for isolation structures. Yet further still, there is a need for a differentiated STI liner process that equalizes stress in N and P-type channels.